1. Technical Field
The present invention relates generally to electrically connected bus interface circuits, and more particularly, to bus interface circuits having signal history controlled pre-emphasis.
2. Description of the Related Art
Interfaces between present-day system devices and also between individual circuits have increased in operating frequency and complexity. In particular, high speed serial bus interfaces typically require sophisticated signal processing in order to achieve maximum bandwidth over cost-effective channel interconnects.
Numerous signaling and reception techniques have been employed to extract the maximum possible data rate from a given channel, for example, feed-forward equalization (FFE) such as signal-history based pre-emphasis/de-emphasis on the transmission side, distributed equalization within the channel in or discrete equalization with respect to the channel characteristics, and receiver-side equalization such as decision feedback equalization, peaking amplifiers, or both linear and adaptive equalizers.
All of the above techniques, although effective, have significant costs in terms of die area, power consumption and complexity. Transmitter-side FFE is most commonly employed, and while desirable, produces sub-optimal signal transmission and reception.
In transmitter-side FFE, the current level provided to interface signal lines is controlled at two or more levels, with the current in intervals where a change in signal value has occurred set to a higher level. In intervals where no change has occurred, the current level is set to a lower current value. Although relatively simple to implement, the transmitter-side FFE current switching scheme yields less than optimal results, in that overshoot typically occurs at the receiver side of the interface for certain data patterns.
It is therefore desirable to provide a bus interface transmitter and transmission method having improved transmitter-side channel equalization characteristics.